The present invention relates to testing individual integrated circuits. In particular, the present invention relates to selectively testing individual chips on a wafer containing multiple chips.
Integrated circuits, and in particular semiconductor integrated circuits, are manufactured by fabricating several individual die or chips on a wafer. The die on a single wafer are typically identical. After fabrication, the wafer is cut up into the individual die. The process of cutting or sawing the wafer into the individual die is called "dicing" the wafer. After the wafer is diced, the individual die are then packaged.
Before the wafer is cut into the individual die, the manufacturer may desire to test the individual die. Such testing permits the manufacturer to discard non-functional die prior to incurring the expense of packaging such defective die.
Typically the individual die are tested by contacting each die on the wafer with a probe device. The probe device contacts test contact pads fabricated on each die, activates the circuitry on the die, and executes a test of the chip. The die failing the test are marked, and are discarded after the wafer is diced.
The current testing methods require that physical probes must be designed and prepared for each different die design, as the points at which the probes must contact the die are different for each die design. The different designs additionally require that the chip tester be physically reconfigured each time a different die design is to be tested.